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Zarlink's Low-Density Circuit Emulation-over-Packet Processors Target Fast Growing Metro Ethernet and Wireless Networks

OTTAWA, Dec. 15 /PRNewswire-FirstCall/ -- Zarlink Semiconductor (NYSE/TSX:ZL) today launched three low-density CES (Circuit Emulation Services)-over-Packet processors that allow network operators to cost- effectively support TDM voice, video and data services over expanding metro Ethernet and wireless networks.

The three-chip ZL(TM)50117 family utilizes CES-over-Packet technology to seamlessly "tunnel" one, two or four streams of TDM traffic, with associated timing and signaling, across Ethernet, IP (Internet Protocol) and MPLS (Multiprotocol Label Switching) networks. Complimenting Zarlink's ZL50120 family of fully featured low-density packet processors, these new devices allow service providers to easily deliver TDM legacy services to their customer.

"By adding Zarlink's CES-over-Packet expertise within a metro Ethernet network, service providers can cost-effectively carry highly profitable TDM traffic alongside packet-based services," said Jeremy Lewis, product line manager, Timing and Convergence, Zarlink Semiconductor. "Similarly, as wireless operators evolve towards an IP infrastructure, CES-over-Packet technology allows them to reduce operating costs and maintain services without requiring a significant infrastructure upgrade."

Legacy services over metro Ethernet

Faced with growing data traffic volumes and increased competition, service providers are aggressively extending flexible metro Ethernet networks closer to the customer. Despite the operating benefits afforded by Ethernet networks, services providers cannot ignore the revenues generated by legacy services from home and enterprise customers.

With Zarlink's new low-density CES-over-Packet devices, network operators rolling out an Ethernet-based network can easily support TDM services. CES-over-Packet allows end customers to maintain their investment in legacy networking equipment and enjoy the lower costs of a packet network, without requiring a "rip and replace" infrastructure overhaul.

All-IP wireless backhaul

Traditionally, wireless network operators have relied on expensive T1/E1 lines to backhaul traffic from base stations to base stations controllers. To reduce operating expenses and meet standards from the 3GPP (3rd Generation Partnership Program) and other organizations, they are now replacing T1/E1 access links with less expensive Gigabit Ethernet-based packet connections.

Zarlink's CES-over-Packet technology can be easily designed into line cards in the base station and base station controller to seamlessly carry TDM traffic across the Ethernet connection. TDM traffic timing information is carried end-to-end across the packet network to ensure service still meets relevant T1/E1 standards.

Similarly, with WiFi (Wireless Fidelity) and WiMAX (Worldwide Interoperability of Microwave Access) technologies gaining acceptance, CES-over-Packet allows the wireless backhaul of T1/E1 trunks across an Ethernet-based local area network at a lower cost than a microwave link.

Synchronization performance

Zarlink has well-established experience delivering TDM-based services to customers, at the system and silicon levels. With these new CES-over-Packet devices, Zarlink has extended this expertise into the packet network. The processors deliver critical synchronization performance that surpasses G.823/G.824 and T1.403 Traffic Interface requirements over a wide variety of packet networks.

Low-density packet processor family

The ZL50117 packet processor family consists of three devices. The ZL50115 chip supports a single T1/E1 stream, the ZL50116 device supports two T1/E1 streams, while the ZL50117 chip supports four T1/E1 streams.

Zarlink's complete CES-over-Packet processor family includes a comprehensive range of lightly- and fully-featured devices capable of handling from one to 32 streams of TDM traffic.

Simplifying design

Zarlink's ZL50117 family simplifies board-level design. With on-chip SRAM (static random access memory) circuitry capable of handling network delays of more than 100 milliseconds and comparable PDVs (packet delay variations), external memory devices are not required. This capability far exceeds customer performance requirements, which range from 10's of milliseconds for network delay up to 10 to 15 seconds of PDV.

Standards compliance

Zarlink's ZL50117 family complies with the ITU's (International Telecommunications Union-Telecommunications) recommendation ITU Y.1413 on TDM-over-MPLS networks, and implementation agreements for Circuit Emulation Services over MPLS and Metro Ethernet networks, from the MPLS-Frame Relay Alliance and the MEF (Metro Ethernet Forum). The processor family also complies with TDM-over-Packet standards under development by the IETF (Internet Engineering Task Force).

Pricing and availability

The ZL50117 packet processors are in volume production. A complete reference design, an evaluation board and a software API (application programming interface) support the chips. All three devices are offered in a 23 mm x 23 mm, 324-ball PBGA (plastic ball grid array) package. In quantities of 5,000, the ZL50115 is priced at US$32.19, the ZL50116 at US$42.63, and the ZL50117 at US$59.16.

For more information on the ZL50117 packet processor, visit http://products.zarlink.com/profiles/ZL50117 . For more on Zarlink's CES-over-Packet expertise, visit http://cesop.zarlink.com/ .

About Zarlink Semiconductor

For almost 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The Company's success is built on its technology strengths, including voice and data networks, consumer and ultra low-power communications, and high-performance analog. For more information, visit http://www.zarlink.com/ .

  Certain statements in this press release constitute forward-looking
  statements within the meaning of the Private Securities Litigation Reform
  Act of 1995. Such forward-looking statements involve known and unknown
  risks, uncertainties, and other factors which may cause the actual
  results, performance or achievements of the Company to be materially
  different from any future results, performance, or achievements expressed
  or implied by such forward-looking statements. Such risks, uncertainties
  and assumptions include, among others, the risks discussed in documents
  filed by the Company with the Securities and Exchange Commission.
  Investors are encouraged to consider the risks detailed in those filings.

  Zarlink, ZL, and the Zarlink Semiconductor logo are trademarks of Zarlink
  Semiconductor Inc.

  A high-resolution photograph is available at
  http://news.zarlink.com/visual_center/ .

CONTACT: Zarlink, Ed Goffin, Media Relations,
(613) 270-7112, edward.goffin@zarlink.com; United States, Natalie Sauve,
High Road Communications, (613) 236-0909, nsauve@highroad.com; Europe,
Simon Krelle, Pinnacle Marketing Communications, 44 1908 2355 22,
simonk@pinnacle-marketing.com

http://www.mentor.com/dsm
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